proFPGA duo XCVU19P System


Technical highlights of the VU19P Prototyping System

  • Scaleable up to 96 M ASIC gates capacity on one board
  • Modular with up to 2 x Xilinx Virtex® XCVU19P FPGAs
  • Up to 3864signals for I/O and inter FPGA connection
  • Up to 28 individually adjustable voltage regions
  • Up to 1.0 Gbps single ended point to point speed

XCVU19P Prototyping System

Product Summary
The proFPGA duo XCVU19P system is a complete and modular multi-FPGA solution, which meets highest requirements in the area of FPGA based Prototyping. It addresses customers who need a scalable and flexible high speed ASIC Prototyping solution for early software development and real time system verification. The innovative system concept offers highest flexibility and reusability reconfigurability for several projects, which guarantees the best return on investment.

Highest Flexibility
The system architecture is based on a modular and scalable single-chip concept. The FPGAs are assembled on dedicated FPGA modules, which will be plugged on the proFPGA uno, duo or quad motherboard. This offers the highest flexibility to use for example different FPGA types in one system or to scale a system in increments of one FPGA. The user has access to almost all I/Os of the FPGA, which gives him maximum freedom regarding the FPGA interconnection structure. This way the prototyping system can be adapted in the best way to any user design. Furthermore the system offers a total of 56 extension sites on the top and bottom site for standard or user specific extension boards like DDR4 memory, PCIe gen4, Gigabit Ethernet, USB 3.0, QSFP28, or other high speed interface and interconnect boards.

Maximum Performance
The well designed boards of the proFPGA system are optimized and trimmed to guarantee best signal integrity and to achieve highest performance. The high speed boards together with specific high speed connectors allow a maximum point-to-point speed of up to 1.0 Gbps single ended over the standard FPGA I/Os and up to 28 Gbps differential over the high speed serial transceivers of the FPGA. This performance combined with the high interconnection flexibility allows the designer to run his design at the highest possible speed in the proFPGA system.

Biggest Capacity
Equipped with up to two Xilinx Virtex® UltraScale+TM VU19P FPGA modules, the proFPGA duo system can handle up to 96 M ASIC gates on only one board. Due to the fact, that multiple proFPGA quad or duo systems can be connected to even larger systems, there is an unlimited scalability and no theoretical maximum in capacity.

Very User Friendly
The proFPGA prototyping system provides an extensive set of features and tools, like remote system configuration, integrated self and performance test, automatic board detection, automatic I/O voltage programming, system scan and safety mechanism, which simplifies the usage of the FPGA based system tremendously.



  • Up to 4 x Xilinx Virtex® XCVU19P FPGA Modules


  • Up to 192 Million ASIC gates on one board (48 Million ASIC gates per FPGA Module)

Signaling rate

  • Up to 1.0 Gbps single ended (standard I/O)/ up to 12.5 Gbps (MGT) differential

Extension sites

  • Up to 16 extension sites with high speed connectors

I/O resources

  • Overall 7728 signals for I/O and inter FPGA connection
    • 1932 free I/Os per FPGA Module
      • 6 x 153 I/Os and 2 x 48 I/Os to top side connectors
      • 6 x 153 I/Os bottom side connectors
      • Single-ended or differential

High Speed I/O transceivers

  • 96 dedicated MGTs running up to 16 Gbps
    • 48 MGTs (up to 28 Gbps) per FPGA Module

FPGAs interconnections

  • Flexible via high-speed interconnection boards or cables

Voltage regions

  • 28 individually adjustable I/O voltage regions
    • 14 individually adjustable voltage regions per FPGA Module
    • Stepless from 1.2 up 1.8V (one site (TA2V1) up to 3.3V)
    • Automated detection of daughter cards and setting of right voltages


  • With host software via Ethernet, USB 2.0, PCIe or standalone over USB stick or JTAG

Clock Management

  • 208 differential external clock inputs
    • 104 differential clock inputs per FPGA Module
      • 12 x 8 and 2 x 4 differential clock inputs per connector
      • Run-time configurable local clocks8 global clock and sync signal inputs per motherboard
      • Fully synchronous derived clocks with sync signals

Data exchange

  • On board DMBI (Device Message Box Interface)

Data exchange rate:

  • Ethernet (up to 100 Mbps)
  • USB (480 Mbps)
  • PCIe (up to 3.5 Gbps)


  • External (optional) ATX Power Supply (12 V, 24 - 35 A output)

System Architechture


proFPGA duo UltraScale+™ XCVU19P FPGA Prototyping System Configurations
 proFPGA duo XCVU19P FM1proFPGA duo XCVU19P FM2
Extension Sites1428
FPGA Modules12
FPGATypeXilinx Virtex® UltraScale+™ XCVU19PXilinx Virtex® UltraScale+™ XCVU19P
Logic Capacity (ASIC Gates)48 M96 M
FPGA Memory75,9 Mbit151,8 Mbit
I/O Resources19323864
High Speed I/O Transceivers4896
Adjustable Voltage Regions1428
Clock Inputs104208
Global Clocks8/x-derived8/x-derived



FPGA Mixing Technology (FMT)

  • Easy plugging and unplugging of FPGA modules on motherboard
  • Various FPGAs from different vendors can be used
  • Automatic scanning and detection of FPGA modules, when plugged
  • Different FPGA configurations are handled and controlled by profpga Messenger

Smart Stacking Technology (SST)

  • Automatic Board detection when boards are plugged
  • Automatic and right I/O voltage setting and programming with conflict detection
  • Integrated interconnection self and performance test
  • Smart I/O resource management. No I/O resources get lost or get blocked by connectors


Device Message Box Interface (DMBI)

  • High speed, low latency data exchange system
  • Enables various use modes like remote system configuration and monitoring and debugging
  • Up to 3.5 Gbps data transfer rate
  • Runs over USB, Ethernet or PCIe


Advanced Clock Management (ACM)

The proFPGA system uses an innovative dual-stage clock generator architecture. Each proFPGA motherboard is capable of distributing up to 8 true asynchronous master beats. Each master beat may be used to derive a virtually unlimited number of clock domains inside the FPGAs. With the unique proFPGA synchronization scheme, clock domains and associated reset signals can be generated fully phase-synchronous over all FPGAs on the motherboard and over multiple motherboards.

FPGA Prototyping Products Overview